1. Field of the Invention
The present invention relates to dynamic logic circuits, and in particular, to dynamic logic circuits operating at low power supply voltages.
2. Description of the Related Art
Referring to FIG. 1, a conventional dynamic clocked inverter latch typically includes two totem-pole-coupled P-MOSFETs between VDD and the output signal node, and two totem-pole-coupled N-MOSFETs between VSS and the output signal node, as shown. The outer N-MOSFET and P-MOSFET devices receive the data input signal DIN, while the inner N-MOSFET and P-MOSFET devices receive the clock signal CLK and its inverse CLKB. Hence, in accordance with the logic level of the data input signal DIN, the output signal DOUT either charges to a logic 1 during the active (low) state of the inverse clock signal CLKB or discharges to a logic 0 during the active (high) state of the clock signal CLK. Referring to FIG. 1A, this operation can be graphically represented as shown.
As MOSFET technology has evolved, individual MOSFETs have become steadily smaller, e.g. with smaller feature sizes, particularly shorter channel lengths. This has allowed more and more MOSFETs to be integrated together in one integrated circuit (IC), as well as allow the requisite power supply voltage (VDD) to become smaller as well. Benefits of the former include reduced size and increased operating frequencies, while benefits of the latter include reduced power consumption. However, operating MOSFETs at today's lower power supply voltages has the undesirable effect of lowering MOSFET current which reduces the maximum operating frequency. Hence, in order to minimize reductions in circuit performance, the MOSFET threshold voltages (V.sub.TH) are reduced so as to minimize reductions in the MOSFET current. (Further discussion of the relationship(s) between power supply voltage, threshold voltage and operating performance for MOSFETs can be found in commonly assigned, copending U.S. patent application Ser. No. 08/292,513, filed Aug. 18, 1994, and entitled "Low Power, High Performance Junction Transistor", the disclosure of which is hereby incorporated herein by reference.) However, this in turn has the undesired effect of increasing MOSFET leakage current, i.e. MOSFET current flowing when the device is turned off. This results in charges leaking to and from the dynamic node(s) of each logic cell which prevents dynamic output signal levels from maintaining their full dynamic charge and discharge voltage levels, thereby decreasing noise immunity and increasing chances of failure due to data losses caused by undesired charges leaking into or desired charges leaking out of the dynamic nodes. Referring to FIG. 1B, the results of such charge leakage in the circuit of FIG. 1 can be graphically represented as shown.
Referring to FIG. 2, an alternative conventional dynamic clocked inverter latch is similar to that of FIG. 1, but with the inputs for the data input signal DIN exchanged with those for the clock signals CLK, CLKB. As with the latch of FIG. 1, this latch also suffers from the effects of increased, undesirable charge leakages when the MOSFET threshold voltages are reduced. However, this latch further suffers from "charge sharing", i.e. the undesired transfer of charges from the dynamic output node to the node between the drain terminals of the P-MOSFETs or the N-MOSFETs when the data input signal DIN is low or high, respectively, during inactive states of the clock signals CLK, CLKB.
Accordingly, it would be desirable to have a dynamic clocked inverter latch with transistors having reduced threshold voltages so as to take maximum advantage of the benefits available from the use of lower power supply voltages while simultaneously minimizing chances of failure due to data losses caused by charge leakage to or from dynamic data storage nodes, minimizing reductions in maximum operating frequency and providing for improved noise immunity.